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ds04-21342-1e fujitsu semiconductor data sheet assp dual serial input pll frequency synthesizer MB15F04 n description the fujitsu MB15F04 is a serial input phase locked loop (pll) frequency synthesizer with two 2.0ghz prescalers. a 64/65 or a 128/129 for both 2.0ghz prescalers can be selected that enables pulse swallow operation. the latest bicmos process technology is used, resuitantly a supply current is limited as low as 11.0ma typ. at a supply voltage of 3.0v. furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. as a result of this, MB15F04 is ideally suitable for digital mobile communications. n features high frequency operation rx synthesizer : 2.0 ghz max. tx synthesizer : 2.0 ghz max. low power supply voltage: v cc = 2.7 to 3.6 v very low power supply current : i cc = 11.0 ma typ. (vcc = 3v) power saving function : i pstx = i pstx = 10 m a max. serial input 14?it programmable reference divider: r = 5 to 16,383 serial input 18?it programmable divider consisting of: - binary 7?it swallow counter: 0 to 127 - binary 11?it programmable counter: 5 to 2,047 on?hip high performance charge pump circuit and phase comparator, achieving high?peed lock?p and low phase noise wide operating temperature: ta = - 40 to 85 c n package 20-pin, plastic ssop (fpt-20p-m03)
2 MB15F04 n pin assignment 1 2 3 4 5 6 20 19 18 17 16 15 7 8 14 gnd rx1 gnd tx ? tx osc in vcc tx ps tx do tx bsc tx clock data le ? rx vcc rx x? rx ps rx do rfx 9 10 13 12 11 (fpt-20p-m03) bs tx x? tx gnd rx2 ld/fout (top view)
3 MB15F04 n pin descriptions pin no. pin name i/o descriptions 1 gnd rx1 ground for rx?ll section. 2 oscin i the programmable reference divider input. tcxo should be connected with a ac coupling capacitor. 3 gnd tx ground for the tx-pll section. 4 fin tx i prescaler input pin for the tx-pll. the connection with vco should be ac coupling. 5 vcc tx power supply voltage input pin for the tx-pll section. when power is off, latched data of tx-pll is cancelled. 6 xfin tx i prescaler complimentary input for the tx-pll section. this pin should be grounded via a capacitor. 7 bsc tx i analog switch output (bs tx ) control for the tx section. always pull-down the bsc tx pin when not using bs tx . (do not leave open.) bsc tx = ?? outputs the do tx state. bsc tx = ? ; goes to high impedance. 8ps tx i power saving mode control for the tx-pll section. this pin must be set at ? power-on. (open is prohibited.) ps tx = ??; normal mode ps tx = ??; power saving mode 9do tx o charge pump output for the tx-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 10 bs tx o analog switch output for the tx selection. 11 gnd rx2 ground 2 for the rx section. 12 do rx o charge pump output for the rx-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 13 ps rx i power saving mode control for the rx-pll section. this pin must be set at ? power-on. (open is prohibited.) ps rx = ? ; normal mode ps rx = ? ; power saving mode 14 ld/fout o lock detect signal output (ld) / phase comparator monitoring output (fout) the output signal is selected by a lds bit in a serial data. lds bit = ? ; outputs fout signal lds bit = ? ; outputs ld signal 15 xfin rx i prescaler complimentary input for the rx-pll section. this pin should be grounded via a capacitor. 16 vcc rx power supply voltage input pin for the rx-pll section. when power is off, latched data of rx-pll is cancelled. 17 fin rx i prescaler input pin for the rx-pll. the connection with vco should be ac coupling. 18 le i load enable signal input (with the schmitt trigger circuit.) when le is ?? data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 data i serial data input (with the schmitt trigger circuit.) a data is transferred to the corresponding latch (tx-ref counter, tx-prog. counter, rx-ref. counter, rx-prog. counter) according to the control bit in a serial data. 20 clock i clock input for the 23-bit shift register (with the schmitt trigger circuit.) one bit data is shifted into the shift register on a rising edge of the clock.
4 MB15F04 n block diagram do tx x? tx ps rf 2 4 18 schmitt circuit 19 schmitt circuit 20 schmitt circuit c n 1 23-bit shift register latch selector 1 v cc rx 16 gnd rx1 ? tx oscin le data clock 5 vcc tx prescaler (tx?ll) 64/65, 128/129 intermittent mode control (tx?ll) c n 2 3-bit latch lds sw tx fc tx binary 7-bit swallow counter (tx?ll) binary 11-bit programmable counter (tx?ll) phase comp. (tx?ll) charge pump (tx?ll) super charger 8 ps tx 7-bit latch 11-bit latch 2-bit latch 14-bit latch binary 14?it pro- grammable ref. counter(tx?ll) 13 17 ? rx prescaler (rx?ll) 64/65, 128/129 3-bit latch lds sw rx fc rx binary 7-bit swallow counter (rx?ll) binary 11-bit programmable counter (rx?ll) charge pump (rx?ll) super charger 7-bit latch 11-bit latch t1 t2 2-bit latch 14-bit latch binary 14-bit pro- grammable ref. counter (rx?ll) t1 t2 or lock det. (tx?ll) lock det. (rx?ll) selector ld fr tx fr rx fp tx fp rx 12 do rx 9 and 14 ld/fout 15 x? rf 3 gnd tx fr tx fr rx ldtx fp rx fp tx intermittent mode control (rx?ll) phase comp. (rx?ll) ldrx 6 bs tx 10 bsc tx 7 analog switch 11 gnd rx2
5 MB15F04 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions handling precautions this device should be transported and stored in anti-static containers. this is a static-sensitive device; take proper anti-esd precautions. ensure that personnel and equipment are properly grounded. cover workbenches with grounded conductive mats. always turn the power supply off before inserting or removing the device from its socket. protect leads with a conductive sheet when handling or transporting pc boards with devices. parameter symbol rating unit remark power supply voltage v cc ?.5 to +4.0 v input voltage v i ?.5 to v cc +0.5 v output voltage v o ?.5 to v cc +0.5 v output current i o ?0 to +10 ma storage temperature t stg ?5 to +125 c parameter symbol value unit note min typ max power supply voltage v cc 2.7 3.0 3.6 v v cctx = v ccrx input voltage v i gnd v cc v operating temperature ta ?0 +85 c
6 MB15F04 n electrical characteristics (v cc = 2.7 v to 3.6 v, ta = ?0 c to +85 c) *1: conditions ; ? tx/rx = 2000 mhz, f osc = 12 mhz, v cctx/rf = 3.0 v, ta = +25 c, in locking state. *2: conditions ; v cctx/rx = 3.0 v, f osc = 12.8 mhz, ta = +25 c *3: ac coupling. the minimum operating frequency is speci?d with a coupling capacitor 1000 pf connected. *4: the symbol (minus) means direction of current ?w. parameter symbol condition value unit min. typ. max. power supply current *1 i cctx tx 5.0 ma i ccrx rx 6.0 power saving current *2 i pstx ps tx =? 0.1* 2 10 m a i psrx ps tx/rx =? 0.1* 2 10 operating frequency ? tx fin tx * 3 tx 100 2000 mhz ? rx fin rx * 3 rx 100 2000 oscin f osc ?40 input sensitivity ? tx vfin tx tx?ll, 50 w load (see test circuit) ?0 +2 dbm ? rx vfin rx rx?ll, 50 w load (see test circuit) ?0 +2 dbm oscin v osc 500 v cc mvp-p input voltage data, clock, le v ih schmitt trigger input v cc x0.7+0.4 v v il schmitt trigger input v cc x0.3?.4 ps tx , ps rx , bsc tx v ih ? cc x0.7 v v il v cc x0.3 input current data, clock, le, ps tx , ps rx , bsc tx i ih *4 ?.0 +1.0 m a i il *4 ?.0 +1.0 oscin i ih 0 +100 m a i il *4 ?00 0 output voltage ld/fout v oh v cc = 3.0v, i oh = ?.0 ma v cc ?.4 v v ol v cc = 3.0v, i ol = 1.0 ma 0.4 do if , do rf , bs tx v doh v cc = 3.0v, i doh = ?.0 ma v cc ?.4 v v dol v cc = 3.0v, i dol = 1.0 ma 0.4 high impedance cutoff current do tx/rx , bs tx i off v cc = 3.0v, v off = gnd to v cc 1.1 m a output current ld/fout i oh *4 v cc = 3.0v ?.0 ma i ol v cc = 3.0v 1.0 do ix , do rx , bs tx i doh *4 v cc = 3.0v, v doh = 2.0v, ta = +25 c ?1 6 ma i dol v cc = 3.0v, v dol = 1.0v, ta = +25 c 815 analog switch on resistance bs tx r on 50 w
7 MB15F04 n functional descriptions the divide ratio can be calculated using the following equation: f vco = {(p x n) + a} x f osc ? r (a < n) f vco : output frequency of external voltage controlled ocillator (vco) p: preset divide ratio of dual modulus prescaler (64 or 128) n: preset divide ratio of binary 11-bit programmable counter (5 to 2,047) a: preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : reference oscillation frequency r: preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of tx/rx?ll sections, programmable reference dividers of tx/rx pll sections are controlled individually. serial data of binary data is entered through data pin. on rising edge of clock, one bit of serial data is transferred into the shift register. when load enable signal is high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. table1. control bit shift register con?uration control bit destination of serial data cn1 cn2 ll the programmable reference counter for the tx-pll. hl the programmable reference counter for the rx-pll. lh the programmable counter and the swallow counter for the tx-pll hh the programmable counter and the swallow counter for the rx-pll programmable reference counter cnt1, 2 : control bit [table. 1] r1 to r14 : divide ratio setting bits for the programmable reference counter (5 to 16,383) [table. 2] t1, 2 : test purpose bit [table. 3] : dummy bit (set to either 0 or 1) note: data input with msb ?st. c n 1 1 2 t 1 3 r 1 4 r 2 5 r 3 6 r 4 7 r 5 8 r 6 9 r 7 10 r 8 11 r 9 12 r 10 13 r 11 14 r 12 15 r 13 16 r 14 17 lsb msb data flow c n 2 t 2 18 x x 19 x 20 x 21 x 22 23
8 MB15F04 table2. binary 14-bit programmable reference counter data setting note: divide ratio less than 5 is prohibited. table.3 test purpose bit setting divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 5 00000000000101 6 00000000000110 16383 11111111111111 t 1 t 2 ld/fout pin state l l outputs fr tx h l outputs fr rx l h outputs fp tx h h outputs fp rx programmable counter c n 1 1 2 l d 3 f c 4 a 1 5 a 2 6 a 3 7 a 4 8 a 5 9 a 6 10 a 7 11 n 1 12 n 2 13 n 3 14 n 4 15 n 5 16 n 6 17 lsb msb data flow c n 2 s w 18 cnt1, 2 : control bit [table. 1] n1 to n14 : divide ratio setting bits for the tx section or rx section programmable counter (5 to 2,047) [table. 4] a1 to a7 : divide ratio setting bits for the tx section or rx section swallow counter (0 to 127) [table. 5] sw tx/rx : divide ratio setting bit for the prescaler (tx section : sw tx , rx section: sw rx ) [table. 6] fc tx/rx : phase control bit for the phase detector (tx section : fc tx , rx section : fc rx ) [table. 7] lds : ld/fout signal select bit [table. 8] note: data input with msb ?st. n 7 n 8 19 n 9 20 n 10 21 n 11 22 23 s tx/ rx tx/ rx
9 MB15F04 table.4 binary 11-bit programmable counter data setting note: divide ratio less than 5 is prohibited. table.5 binary 7-bit swallow counter data setting note: divide ratio (a) range = 0 to 127 table. 6 prescaler data setting divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 5 00000000101 6 00000000110 2047 11111111111 divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 127 1111111 sw = ? sw = ? prescaler divide ratio tx-pll 64/65 128/129 rx-pll 64/65 128/129
10 MB15F04 table. 7 phase comparator phase switching data setting note: z = high?mpedance depending upon the vco and lpf polarity, fc bit should be set. table. 8 ld/fout output select data setting serial data input timing fc = h fc = l fr > fp h l fr = fp z z fr < fp l h vco polarity (1) (2) lds ld/fout output signal h fout (fr tx/rx , fp tx/rx ) signals l ld signal vco output voltage vco output frequency (1) (2) parameter unit max typ min t 1 t 2 t 3 t 4 ns ns ns ns 20 20 30 20 30 100 100 parameter unit max typ min t 5 t 6 t 7 ns ns ns on rising edge of the clock, one bit of the data is transferred into the shift register. data clock le msb lsb 1st. data 2nd. data invalid data control bit t 1 t 0 t 2 t 5 t 3 t 6 t 4
11 MB15F04 n phase detector output waveform note: phase error detection range = - 2 p to +2 p pulses on do tx/rx signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on oscin input frequency as follows. t wu > 8/fosc: i.e. t wu > 625ns when foscin = 12.8 mhz t wl < 16/fosc: i.e. t wl < 1250ns when foscin = 12.8 mhz t wu fr tx/rx fp tx/rx t wl ld (fc bit = high) do tx/rx z l (fc bit = low) z h do tx/rx tx?ll section rx?ll section ld output locking state / power saving state locking state / power saving state locking state / power saving state h l l l unlocking state unlocking state unlocking state locking state / power saving state unlocking state ld output logic table
12 MB15F04 n power saving mode (intermittent mode control circuit) setting a ps tx(rx) pin to low, tx-pll (rx-pll) enters into power saving mode resultant current consumption can be limited to 0.1 m a (typ.). setting ps pin to high, power saving mode is released so that the device works normally. in addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. in general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. such case, if the pll is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an unde?ed phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. to prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up. thus keeping the loop locked. ps pin must be set ? at power-on. allow 1 m s after frequency stabilization on power-up for exiting the power saving mode (ps: l to h) serial data can be entered during the power saving mode. during the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 m a per one pll section. at that time, the do and ld become the same state as when a loop is locking. that is, the do becomes high impedance. a vco control voltage is naturally kept at the locking voltage which de?ed by a lpfs time constant. as a result of this, vcos frequency is kept at the locking frequency. ps tx ps rx tx-pll counters rx-pll counters osc input buffer l l off off off h l on off on l h off on on h h on on on
13 MB15F04 n analog switch (bsc tx pin) the analog switch is set on or off by the bsc tx input. when the switch is on, the output of the charge pump (do tx ) is output from the bs tx pin. (the pin goes to high impedance when the switch is off.) as in the example shown in the ?ure below, placing the analog switch midway through the lpf (lpf1 + lpf2) allows the lpf time constant to be reduced during pll channel switching so as to speed up the lock up time. analog switch bsc tx on h off l chp lpf1 lpf2 vco analog swtch do tx bs tx bsc tx
14 MB15F04 n typical characteristics (continued) input sensivity of fin (rx) vs. input frequency input sensivity of osc vs. input frequency input sensivity of fin (tx) vs. input frequency 10 5 0 ? ?0 ?5 ?0 ?5 ?0 vfin rx (dbm) spec ta = +25 c v cc =2.7 v v cc =3.0 v v cc =3.6 v ?5 ?0 0 1000 2000 3000 4000 fin (mhz) v osc ( dbm0) 10 0 ?0 ?0 ?0 ?0 ?0 ?0 10 50 100 0 ta = +25 c v cc =2.7 v v cc =3.0 v v cc =3.6 v spec f osc (mhz) 10 5 0 ? ?0 ?5 ?0 ?5 ?0 vfin tx (dbm) ta = +25 c v cc =2.7 v v cc =3.0 v v cc =3.6 v ?5 ?0 0 1000 2000 3000 4000 spec fin (mhz)
15 MB15F04 (continued) rx do output current conditions: ta = +25 c .0000 .0000 v doh ( v) i doh (ma) ?5.00 5.000 v cc = 3 v ta = +25 c i doh ?v doh v dol ( v) i dol (ma) .0000 .0000 25.00 5.000 v cc = 3 v ta = +25 c i dol ?v dol
16 MB15F04 (continued) tx do output current conditions: ta = +25 c .0000 .0000 v doh ( v) i doh (ma) ?5.00 5.000 v cc = 3 v ta = +25 c i doh ?v doh v dol ( v) i dol (ma) .0000 .0000 25.00 5.000 v cc = 3 v ta = +25 c i dol ?v dol
17 MB15F04 (continued) input impedance ? rx pin ? tx pin 9.7188 w ?7.062 w 500 mhz 8.2324 w ?7.395 w 1 ghz 11.075 w 6.2979 w 1.5 ghz 12.635 w 23.558 w 2 ghz 1 ; 2 ; 3 ; 4 ; f in 4 3 1 2 start 100.000 000 mhz stop 1 500.000 000 mhz 19.266 w ?32.09 w 500 mhz 9.6855 w ?9.215 w 1 ghz 11.299 w ?3.364 w 1.5 ghz 12.398 w 10.659 w 2 ghz 1 ; 2 ; 3 ; 4 ; f in 4 3 1 2 start 100.000 000 mhz stop 1 500.000 000 mhz
18 MB15F04 (continued) input impedance oscin pin 28.862 k w ?3.732 k w 1 mhz 77 w ?.5602 k w 12.8 mhz 114.63 w ?.5294 k w 23 mhz 112.13 w ?.9848 k w 30 mhz 1 ; 2 ; 3 ; 4 ; osc in start .500 000 mhz stop 100.000 000 mhz 2 4 3
19 MB15F04 n test circuit (prescaler input/programmable reference divider input sensitivity test) MB15F04 1 2 5 4 73 10 6 8 9 16 15 14 12 13 11 17 19 18 20 s.g s.g vcc tx 0.1 m f 1000pf 50 w 1000pf s.g 50 w 1000p 50 w 1000pf 0.1 m f vcc rx 1000 pf controller (sets the divide ratios) oscilloscope gnd
20 MB15F04 n application example vco low pass tcxo 3 v 1000 pf 0.1 m f 1000 pf 18 17 16 15 14 13 12 11 12 3 4 5 6 7 8 3 v 0.1 m f 1000 pf 1000 pf vco low pass output lock det. clock, data, le: schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input). MB15F04 9 10 19 20 1000 pf output ?ter ?ter bsctx : always pull-down the bsctx pin when not using the analog switch output (bs tx ). (do not leave the pin open.) from controller
21 MB15F04 n ordering information part number package remarks MB15F04 pfv 20pin, plastic ssop (fpt-20p-m03)
22 MB15F04 n package dimension +0.20 C0.10 +.008 C.004 +0.10 C0.05 +.004 C.002 +0.05 C0.02 +.002 C.001 index "a" 0.10(.004) 1.25 .049 0.22 .009 0.15 .006 (.0256.0047) * (.173.004) (.252.008) nom 6.400.20 4.400.10 5.40(.213) 0.650.12 * 6.500.10(.256.004) 5.85(.230)ref details of "a" part 0 10 (stand off) 0.100.10(.004.004) (.020.008) 0.500.20 1994 fujitsu limited f20012s-2c-4 c dimensions in mm (inches) 20 pins, plastic ssop (fpt-20p-m03) * : these dimensions do not include resin protrusion.
23 MB15F04 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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